Source

SCPI Command :

LANE<*>:EQUalization:DFE:TIMReference:CLOCk:SOURce

Commands in total: 1
Subgroups: 0
Direct child commands: 1

get(lane=Lane.Default) → SignalSource[source]

# LANE<*>:EQUalization:DFE:TIMReference:CLOCk:SOURce
value: enums.SignalSource = driver.lane.equalization.dfe.timReference.clock.source.get(lane = repcap.Lane.Default)

Selects the source of the clock channel, if method RsRtx.lane.equalization.dfe.timReference.source.set() is set to CLOCk.

Parameters:: lane – optional repeated capability selector. Default value: Nr1 (settable in the interface ‘Lane’)
Returns:: clock_source: C1W1 | C1W2 | C1W3 | C2W1 | C2W2 | C2W3 | C3W1 | C3W2 | C3W3 | C4W1 | C4W2 | C4W3 | M1 | M2 | M3 | M4 | R1 | R2 | R3 | R4 | DIFF1 | DIFF2 | COMMON1 | COMMON2 | M5 | M6 | M7 | M8

set(clock_source: SignalSource, lane=Lane.Default) → None[source]

# LANE<*>:EQUalization:DFE:TIMReference:CLOCk:SOURce
driver.lane.equalization.dfe.timReference.clock.source.set(clock_source = enums.SignalSource.AJ1, lane = repcap.Lane.Default)

Selects the source of the clock channel, if method RsRtx.lane.equalization.dfe.timReference.source.set() is set to CLOCk.

Parameters:

clock_source – C1W1 | C1W2 | C1W3 | C2W1 | C2W2 | C2W3 | C3W1 | C3W2 | C3W3 | C4W1 | C4W2 | C4W3 | M1 | M2 | M3 | M4 | R1 | R2 | R3 | R4 | DIFF1 | DIFF2 | COMMON1 | COMMON2 | M5 | M6 | M7 | M8
lane – optional repeated capability selector. Default value: Nr1 (settable in the interface ‘Lane’)